1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the device, particularly relates to a packaging technique of a semiconductor device having a power transistor.
2. Description of Related Art
A high-power semiconductor device includes a semiconductor device having a semiconductor chip in which a power transistor such as power MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor), IGBT (Insulated Gate Bipolar Transistor), and bipolar power transistor is formed.
The semiconductor device having such a power transistor is described in, for example, International Patent Application No. W2001/075961 (patent literature 1) which discloses a structure of a semiconductor device having the power MOS FET. The paragraph 0024 and FIG. 21 of the patent literature 1 disclose a configuration in which a drain electrode of a die (semiconductor chip) is connected to a surface of an inner web in a clip by epoxy containing silver, and optimally epoxy having low stress and high adhesive force is coated around an edge of a die in a ring pattern to seal a package and add structural strength to the package.
Moreover, for example, JP-A-2003-51513 (patent literature 2) discloses a configuration in which an electrode of a semiconductor chip having a power MOS FET is connected with a metal strip. The paragraph 0041 and FIG. 5 of the patent literature 2 disclose a configuration in which the metal strip is directly bonded onto an electrode pad of a semiconductor device (semiconductor chip) using ultrasonic energy, and furthermore periphery of the bonded portion between the electrode pad and the metal strip is sealed by moisture-resistant resin having flexibility, moisture resistance and heat resistance.
[Patent literature 1] International Patent Application No. W 2001-075961 (paragraph 0024 and FIG. 20).
[Patent literature 2] JP-A-2003-51513 (paragraph 0012, 0041, FIG. 5 and the like).